Hardware acceleration for software emulation of pci express compliant devices

Abstract

A system that provides virtualized computing resources may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware in software. The endpoint device may include host interface circuitry that implements pointer registers and control and status registers for each of multiple transaction ring buffers instantiated in memory on the device. In response to receiving a transaction layer packet that includes a transaction, packet steering circuitry may push the transaction into one of the buffers, dependent on the transaction type, a routing identifier for an emulated device to which it is directed, its traffic class or other criteria. The transaction may be processed in software, emulating the hardware device. The host interface circuitry may generate response completion packets for configuration requests and non-posted transactions, and may return them according to PCIe ordering rules, regardless of the order in which they were processed on the endpoint device.