The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Feb. 08, 2016
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

John J. Walsh, Tampa, FL (US);

John Ross Wallrabenstein, West Lafayette, IN (US);

Hal A. Aldridge, Tampa, FL (US);

Michael J. Duren, Oldsmar, FL (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/44 (2013.01); H04L 9/32 (2006.01); H04L 29/06 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 21/44 (2013.01); H04L 9/0866 (2013.01); H04L 9/3242 (2013.01); H04L 9/3278 (2013.01); H04L 63/08 (2013.01); H04L 63/0876 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A resilient device authentication system for use with one or more managed devices each including a physical unclonable function (PUF), comprises: one or more verification authorities (VA) each including a processor and a memory loaded with a complete verification set (CVS) that includes hardware part-specific data associated with the managed devices' PUFs and metadata, the processor configured to create a limited verification set (LVS) through one-way algorithmic transformation of hardware part-specific data together with metadata from the loaded CVS so as to create a LVS representing both metadata and hardware part-specific data adequate to redundantly verify all of the hardware parts associated with the LVS; and one or more provisioning entities (PE) each connectable to a VA and including a processor and a memory loaded with a LVS, and configured to select a subset of the LVS so as to create an application limited verification set (ALVS). The system may also comprise one or more device management systems each connectable to a PE and to managed devices and including a memory configured to store an ALVS. The VA may also be configured to create a replacement LVS.


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