The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jun. 28, 2016
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Ali Saidi, Austin, TX (US);

Kshitij Sudan, Austin, TX (US);

Andrew Joseph Rushing, Austin, TX (US);

Andreas Hansson, Cambridge, GB;

Michael Filippo, Driftwood, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0871 (2016.01); G06F 12/0873 (2016.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 12/0873 (2013.01); G06F 12/0895 (2013.01); G06F 2212/305 (2013.01); G06F 2212/401 (2013.01); G06F 2212/466 (2013.01);
Abstract

Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.


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