The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Nov. 08, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do OT, KR;

Inventors:

Jingyu Kang, San Jose, CA (US);

Chung-Li Wang, Fremont, CA (US);

Cai Wang, San Jose, CA (US);

Yibo Zhang, San Jose, CA (US);

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/13 (2006.01); H03M 13/27 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0665 (2013.01); G06F 3/0679 (2013.01); G06F 11/1044 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/13 (2013.01); H03M 13/2757 (2013.01);
Abstract

Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.


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