The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Oct. 24, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Charles J. Camp, Sugar Land, TX (US);

Timothy J. Fisher, Cypress, TX (US);

Kevin E. Sallese, Fulshear, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/10 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0614 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/10 (2013.01); G06F 3/0638 (2013.01); G06F 12/1027 (2013.01); G06F 2212/152 (2013.01); G06F 2212/214 (2013.01); G06F 2212/651 (2013.01); G06F 2212/657 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01);
Abstract

A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.


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