The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Jun. 26, 2017
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Jinda Yang, Shanghai, CN;

Liren Zhou, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/66 (2006.01); H03M 1/74 (2006.01); H03M 1/42 (2006.01); H03M 1/38 (2006.01); H03M 1/76 (2006.01); G10L 15/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/747 (2013.01); G10L 15/12 (2013.01); H03M 1/1205 (2013.01); H03M 1/38 (2013.01); H03M 1/42 (2013.01); H03M 1/76 (2013.01);
Abstract

An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.


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