The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

May. 17, 2013
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Juergen Holz, Wenzenbach, DE;

Michael Zitzlsperger, Regensburg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/54 (2010.01); H01L 33/50 (2010.01); H01L 33/48 (2010.01); H01L 25/075 (2006.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 33/54 (2013.01); H01L 33/486 (2013.01); H01L 33/505 (2013.01); H01L 25/0753 (2013.01); H01L 33/62 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48471 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0091 (2013.01);
Abstract

An optoelectronic component includes a housing having a first cavity open toward an upper side of the housing, and a second cavity open toward the upper side of the housing, wherein the first cavity and the second cavity connect by a connecting channel, an optoelectronic semiconductor chip is arranged in the first cavity, a potting material is arranged in a region of the first cavity enclosing the optoelectronic semiconductor chip, a bond wire is arranged between an electrical contact surface of the optoelectronic semiconductor chip and a bond surface of the housing, and the bond surface is arranged in the connecting channel.


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