The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Dec. 09, 2015
Applicant:

The Royal Institution for the Advancment of Learning/mcgill University, Montreal, CA;

Inventors:

Guillaume Gervais, Monteral, CA;

Keyan Bennaceur, Sherbrooke, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/66 (2006.01); H01L 29/82 (2006.01); H01L 29/205 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/772 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7606 (2013.01); H01L 29/66977 (2013.01); H01L 29/1025 (2013.01); H01L 29/205 (2013.01); H01L 29/778 (2013.01); H01L 29/7727 (2013.01); H01L 29/82 (2013.01);
Abstract

High electron mobility leads to better device performance and today is achieved by fabricating 'gated devices' within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and 'zero' DEG structures.


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