The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Jan. 20, 2017
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventor:

Hiromitsu Takeda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 21/4846 (2013.01); H01L 24/45 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/10161 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1515 (2013.01); H01L 2924/1579 (2013.01); H01L 2924/15183 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15738 (2013.01); H01L 2924/181 (2013.01); H01L 2924/186 (2013.01); H01L 2924/3512 (2013.01);
Abstract

The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.


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