Systems and methods for analyzing soft errors in a design and reducing the associated failure rates thereof

Abstract

Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design. Another such method involves using the design and a list of memories that need error correction code inserted automatically and limiting the impact to the clock cycle, by analyzing the timing to the inputs and from the outputs of the memories and inserting an in-line or a late timing wrapper, which includes the ECC insert during writes, and ECC check and correct during reads, identifying the registers that need to be shadowed and used in the delayed ECC correct cycle, identifying the clock gating required for various elements in the design to get the correct logic at the conclusion of the re-play cycle of ECC correction in case of late timing ECC correction.