The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Sep. 03, 2014
Applicant:

Longitude Semiconductor S.a.r.l., Luxembourg, LU;

Inventors:

Yoshinori Matsui, Luxembourg, LU;

Toshio Sugano, Luxembourg, LU;

Hiroaki Ikeda, Luxembourg, LU;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/408 (2006.01); G11C 5/00 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/26 (2006.01); G11C 29/48 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); G11C 8/12 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
G11C 11/408 (2013.01); G11C 5/00 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 7/1051 (2013.01); G11C 7/1063 (2013.01); G11C 8/12 (2013.01); G11C 29/1201 (2013.01); G11C 29/26 (2013.01); G11C 29/48 (2013.01); H01L 23/5384 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/00014 (2013.01);
Abstract

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.


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