The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Dec. 13, 2017
Applicant:

Tactotek Oy, Oulunsalo, FI;

Inventors:

Hasse Sinivaara, Oulunsalo, FI;

Tuomas Heikkilä, Oulunsalo, FI;

Antti Keränen, Oulunsalo, FI;

Assignee:

TACTOTEK OY, Oulunsalo, FI;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G05B 19/4099 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5018 (2013.01); G06F 17/5081 (2013.01); G05B 19/4099 (2013.01); G05B 2219/45031 (2013.01); G06F 2217/02 (2013.01); G06F 2217/04 (2013.01); G06F 2217/06 (2013.01); G06F 2217/12 (2013.01);
Abstract

An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.


Find Patent Forward Citations

Sinivaara, Hasse. (2018). Arrangement and method for facilitating electronics design in connection with 3d structures (U.S. Patent No. 9990455). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9990455

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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