The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2018
Filed:
Aug. 12, 2014
Applicant:
Empire Technology Development Llc, Wilmington, DE (US);
Inventor:
Yan Solihin, Raleigh, NC (US);
Assignee:
EMPIRE TECHNOLOGY DEVELOPMENT LLC, Wilmington, DE (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/12 (2016.01); G11C 7/10 (2006.01); G06F 12/0831 (2016.01); G06F 12/0811 (2016.01); G11C 11/401 (2006.01); G11C 11/406 (2006.01); G06F 12/123 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0833 (2013.01); G06F 12/0811 (2013.01); G11C 7/1072 (2013.01); G11C 11/40607 (2013.01); G11C 11/40622 (2013.01); G06F 12/123 (2013.01); G06F 2212/1024 (2013.01); G11C 11/401 (2013.01); G11C 11/406 (2013.01); Y02D 10/13 (2018.01);
Abstract
Techniques described herein generally include methods and systems related to improving energy efficiency in a chip multiprocessor by reducing the energy consumption of a DRAM cache for such a multi-chip processor. Methods of varying refresh interval may be used to improve the energy efficiency of such a DRAM cache. Specifically, a per-set refresh interval based on retention time of memory blocks in the set may be determined, and, starting from the leakiest memory block, memory blocks stored in the DRAM cache that are associated with data also stored in a lower level of cache are not refreshed.