The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Sep. 24, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hien Minh Le, Cedar Park, TX (US);

Thuong Quang Truong, Austin, TX (US);

Kun Xu, Austin, TX (US);

Jaya Prakash Subramaniam Ganasan, Youngsville, NC (US);

Cesar Aaron Ramirez, Hutto, TX (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0831 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 12/0815 (2016.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 12/0815 (2013.01); G06F 13/16 (2013.01); G06F 13/4027 (2013.01); G06F 13/42 (2013.01); G06F 9/524 (2013.01); G06F 12/0833 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/621 (2013.01);
Abstract

Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.


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