Memory tracking using copy-back cache for 1:1 device redundancy

Abstract

A redundant process controller arrangement includes a primary controller and parallel connected secondary controller each coupled to actuators and sensors coupled to processing equipment. The primary and secondary controllers include a main writable memory including a cache data control algorithm, central processing unit (CPU) with cache memory including cache not supporting write-thru, tracker logic coupled to a control cycle database in a tracked memory region and to a primary tracking buffer. A redundancy link is between the CPUs for passing tracked changes. The algorithm implements memory tracking using copy-back including the primary tracker logic each cycle writing tracked changes into the primary tracking buffer, and at cycle end, transferring tracked changes from the primary tracking buffer to the secondary controller over the redundancy link, and writing tracked changes to the secondary control database.