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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9990139 B1

PDFFull Text
Date of Patent:
Jun. 05, 2018

Filed:

Jan. 04, 2016

Scalable and area optimized method to implement command queues in sriov based nvm devices

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Srinivasa Raju Nadakuditi, Karnataka, IN;

Madhusudan Sampath, Karnataka, IN;

Sarath Kumar Kunnumpurathu Sivan, Kerala, IN;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:

F. Chau & Associates, LLC

Primary Examiner:

Faisal M Zaman

Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/12 (2006.01); G06F 13/38 (2006.01); G06F 13/20 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 9/455 (2018.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 9/45558 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); H04L 41/0654 (2013.01); H04L 41/0681 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

Provided are method for dynamically allocating resources to command queues and response queues by a non-volatile memory (NVM) controller. The method includes creating command queues and response queues for at least one operating system among a plurality of operating systems running on a host system and mapping the created command queues and response queues to a plurality of internal shared queue registers. The plurality of operating systems running on the host system communicate with at least one NVM controller independently.

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