The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Jan. 23, 2017
Applicant:

Samsung Display Co., Ltd, Yongin-si, Gyeonggi-do, KR;

Inventors:

Young Jae Jeon, Asan-si, KR;

Il You, Seongnam-si, KR;

Seung Rae Kim, Cheonan-si, KR;

Chun Yan Jin, Hwaseong-si, KR;

Beom Soo Park, Hwaseong-si, KR;

Jae Hyun Park, Yongin-si, KR;

Sang Ju Lee, Seoul, KR;

Hye Won Hyeon, Anseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 27/1248 (2013.01); H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/42384 (2013.01); H01L 29/78636 (2013.01); H01L 29/78696 (2013.01); G02F 2001/134318 (2013.01); H01L 2029/42388 (2013.01);
Abstract

A display device is provided. The display device includes a base; a gate conductor disposed directly on the base and including a gate line and a gate electrode; a gate insulating layer disposed on the gate conductor and including an overlap portion, which overlaps with the gate conductor, and a non-overlap portion, which is connected to the overlap portion, does not overlap with the gate conductor, and is spaced apart from the base; and a semiconductor pattern disposed on the gate insulating layer and overlapping with the gate electrode, wherein edges of the gate insulating layer project further than edges of the gate conductor and edges of the semiconductor pattern.


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