The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Oct. 27, 2016
Applicants:

Arm Limited, Cambridge, GB;

University of Southampton, Southampton, GB;

Inventors:

Anand Savanth, Cambridge, GB;

James Edward Myers, Bottisham, GB;

Yunpeng Cai, Southampton, GB;

Alexander Stewart Weddell, New Milton, GB;

Tom Kazmierski, Southampton, GB;

Assignees:

ARM Limited, Cambridge, GB;

University of Southampton, Southamptonn, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/3562 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); H03K 19/20 (2013.01);
Abstract

A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.


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