The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jan. 25, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sang Woo Kim, Suwon-si, KR;

Suk Nam Kwon, Seongnam-si, KR;

Jin Ook Song, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/012 (2013.01);
Abstract

A semiconductor device includes a power gating circuit including a synchronous reset flip-flop, a retention circuit including a retention flip-flop, a clock management circuit configured to provide an operation clock to the power gating circuit and the retention circuit, and a power management circuit configured to transmit a power gating control signal to the power gating circuit, the retention circuit, and the clock management circuit. The power gating circuit is activated to signal entry to a power reduction mode. The retention circuit retains states of the semiconductor device. Upon exit from the power reduction mode, the power management circuit is configured to complete a reset operation of the power gating circuit before signaling the retention circuit to cancel a retention state and restore the states of the semiconductor device.


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