The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Oct. 30, 2013
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, Tokyo, JP;

Inventors:

Yuruki Okada, Tokyo, JP;

Yoshinori Yamashita, Tokyo, JP;

Sho Kato, Tokyo, JP;

Hisanori Yamasaki, Tokyo, JP;

Assignee:

MITSUBISHI ELECTRIC CORPORATION, Chiyoda-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); H02M 1/00 (2006.01); H02M 7/487 (2007.01); H02M 3/158 (2006.01); B60L 9/22 (2006.01); B60L 11/18 (2006.01); B60L 15/00 (2006.01); H02M 1/08 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); B60L 9/22 (2013.01); B60L 11/1864 (2013.01); B60L 15/007 (2013.01); H02M 1/08 (2013.01); H02M 7/487 (2013.01); B60L 2200/26 (2013.01); B60L 2210/10 (2013.01); B60L 2210/40 (2013.01); B60L 2240/527 (2013.01); H02M 3/1584 (2013.01); H02M 2001/0009 (2013.01); Y02T 10/645 (2013.01); Y02T 10/7005 (2013.01); Y02T 10/7061 (2013.01); Y02T 10/7216 (2013.01); Y02T 10/7241 (2013.01);
Abstract

A DC/DC conversion device that includes three-level power conversion circuits in a plurality of phases. The DC/DC conversion device includes voltage detectorsandthat detect at least two voltages (Efc and EfcL) of an input DC voltage, a first divided voltage, and a second divided voltage; and a voltage control unitthat controls an output voltage of three-level power conversion circuitsand. At least one phase (the power conversion circuit) of the three-level power conversion circuitsandoperates as an imbalance-reduction phase that executes imbalance-reduction control such that one (EfcL) of the first and second divided voltages is divided into half of the input DC voltage Efc.


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