The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9985428 B1

PDF
Full Text
Expired
Date of Patent:
May. 29, 2018

Filed:

Sep. 09, 2016
Applicants:

Xj Group Corporation, Xuchang, Henan, CN;

Xj Electric Co., Ltd, Xuchang, Henan, CN;

Xuchang Xj Software Technology Co., Ltd, Xuchang, CN;

State Grid Corporation of China, Beijing, CN;

Inventors:

Jirui Chen, Xuchang, CN;

Maojun Deng, Xuchang, CN;

Chuankun Ni, Xuchang, CN;

Lijuan Lv, Xuchang, CN;

Heke Ma, Xuchang, CN;

Dongxiao Yao, Xuchang, CN;

Baowei Li, Xuchang, CN;

Xu Li, Xuchang, CN;

Jidong Huang, Xuchang, CN;

Feng Xiao, Xuchang, CN;

Shasha Hu, Xuchang, CN;

Jingli Zhang, Xuchang, CN;

Yingying Xi, Xuchang, CN;

Assignees:

XJ Group Corporation, Xuchang, Henan Province, CN;

XJ Electric Co., Ltd., Xuchang, Henan Province, CN;

Xuchang XJ Software Technology Co., Ltd., Xuchang, Henan Province, CN;

State Grid Corporation of China, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 7/26 (2006.01);
U.S. Cl.
CPC ...
H02H 7/261 (2013.01);
Abstract

Sampling implementation method and device based on conventional sampling GOOSE trip mode. CPU of master NPI plug-in, after receiving a second pulse, transmits sampling pulse generation time and a transmission enable bit to FPGA of the master NPI plug-in at a fixed interval; after detecting the transmission enable bit, the FPGA of the master NPI plug-in judges whether time of its internal timer is greater than/equal to the sampling pulse generation time, if yes, generates a sampling pulse to FPGA of collection plug-in; after receiving sampling pulse, the collection plug-in carries out A/D sampling, and transmits sampled data to the master NPI plug-in; when detecting that all A/D samplings are completed, the master NPI plug-in transmits data packets to protection CPU plug-in. The device includes an MMI plug-in, a protection CPU plug-in, a master NPI plug-in and a collection plug-in. Protection maloperation is thereby reduced.


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