The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

May. 23, 2014
Applicant:

Hrl Laboratories Llc., Malibu, CA (US);

Inventors:

David T. Chang, Calabasas, CA (US);

Frederic P. Stratton, Beverly Hills, CA (US);

Hung Nguyen, Los Angeles, CA (US);

Randall L. Kubena, Oak Park, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 41/311 (2013.01); H01L 41/053 (2006.01); H01L 41/047 (2006.01); H01L 41/23 (2013.01); H01L 41/29 (2013.01); H01L 41/332 (2013.01);
U.S. Cl.
CPC ...
H01L 41/311 (2013.01); H01L 41/0475 (2013.01); H01L 41/053 (2013.01); H01L 41/23 (2013.01); H01L 41/29 (2013.01); H01L 41/332 (2013.01);
Abstract

High-yield fabrication methods are provided for making quartz resonators having thicknesses ranging from one micrometer to several hundred micrometers and thus covering the frequency range from HF to UHF. Plasma dry etching is used to form arbitrary resonator geometries. The quartz resonator structure and the through-quartz vias are formed concurrently. The method includes bonding a quartz device wafer to a quartz handle wafer with a temporary adhesive. Mesa structures formed by plasma dry etching enable the resonators to achieve high-Q operation with energy trapping/mode confinement. A thermo-compression bond integrates the quartz resonators to a host wafer (e.g., an oscillator ASIC) to form oscillators. Silicon cap wafers are bonded over the resonators to the ASIC to provide wafer scale hermetic encapsulation of the quartz oscillators.


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