The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jun. 27, 2014
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Yasushi Takaki, Tokyo, JP;

Yoichiro Tarui, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/739 (2006.01); H01L 29/12 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 21/26513 (2013.01); H01L 29/0696 (2013.01); H01L 29/086 (2013.01); H01L 29/1045 (2013.01); H01L 29/12 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/739 (2013.01); H01L 29/78 (2013.01);
Abstract

The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer, a well region, a source region, a channel resistance adjusting region, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The channel resistance adjusting region is sandwiched between the source region and the SiC epitaxial layer in a surface layer of the well region. The channel resistance adjusting region is a region in which a first impurity region is intermittently formed in a direction intersecting a direction in which the source region and the SiC epitaxial layer sandwich the channel resistance adjusting region.


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