The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2018
Filed:
Apr. 11, 2016
Applicant:
Hrl Laboratories, Llc, Malibu, CA (US);
Inventor:
Kenneth R. Elliott, Thousand Oaks, CA (US);
Assignee:
HRL Laboratories, LLC, Malibu, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/15 (2006.01); H01L 29/43 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7784 (2013.01); H01L 29/157 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/432 (2013.01); H01L 29/66462 (2013.01);
Abstract
A FET device includes a substrate having top and bottom surfaces, a channel layer on the top surface of the substrate; the channel layer having top and bottom surfaces, at least two recesses extending into the channel layer from the top surface of the channel layer and forming a channel region between the at least two recesses, a gate electrode disposed in each of the at least two recesses, and a drain region and a source region formed in the channel layer on opposite sides of said channel region.