The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Sep. 21, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co., Ltd., Anhui, CN;

Inventors:

Chuanbao Chen, Beijing, CN;

Juncai Ma, Beijing, CN;

Jie Yang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); G02F 1/1345 (2006.01); G02F 1/1368 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); G02F 1/1368 (2013.01); G02F 1/13454 (2013.01); G02F 1/133345 (2013.01); G02F 1/133514 (2013.01); G02F 1/136286 (2013.01); G02F 2001/136295 (2013.01);
Abstract

The present disclosure provides an array substrate and a display device that can suppress the adverse effects in display due to difference in gray-scale luminance of adjacent two rows caused by variation in capacitance of adjacent two rows of TFTs as the result of displacement of the data lines. Scan lines and data lines crossing each other are arranged on the array substrate. Each row of the scan lines is provided with a gate driver circuit, wherein each row of the scan lines is further provided with a compensation capacitor connected to the gate driver circuit, the compensation capacitor including a first metal layer and a second metal layer that are overlapped with each other to form an overlap region at which the first metal layer is isolated from the second metal layer by an insulation layer, wherein the compensation capacitor in an Nrow has a capacitance that changes in a direction opposite to the direction in which the capacitance of the compensation capacitor in an N+1row changes, and the compensation capacitor in the Nrow has a capacitance that changes in the same direction as the direction in which the capacitance of a thin film transistor capacitor in the N+1row changes, where N is a natural number greater than or equal to 1.


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