The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jun. 21, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Seung Cheol Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 21/76814 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 28/00 (2013.01);
Abstract

Disclosed is a method of manufacturing a semiconductor device, including: forming a multi-layered stack; forming a vertical hole in the stack; forming a plurality of material layers over a bottom and a sidewall of the vertical hole, wherein the plurality of material layers includes a first material layer and a second material layer, wherein the second material layer is provided under the first material layer; patterning the first material layer located over the bottom of the vertical hole to form a first opening, wherein the first opening exposes the second material layer; and patterning the second material layer exposed by the first opening using a difference in an etch rate between the first material layer and the second material layer.


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