The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Apr. 27, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Shibun Tsuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 27/0886 (2013.01); H01L 27/11573 (2013.01); H01L 29/42348 (2013.01); H01L 29/7851 (2013.01); H01L 29/792 (2013.01);
Abstract

An improvement is achieved in the reliability of a semiconductor device. In a memory cell region, a plurality of fins are provided which are portions of a semiconductor substrate extending in an x-direction along a main surface of the semiconductor substrate and spaced apart from each other in a y-direction orthogonal to the x-direction along the main surface of the semiconductor substrate. Between the fins adjacent to each other in the y-direction, a portion of an upper surface of an isolation region is at a position higher than a surface obtained by connecting a position of the upper surface of the isolation region which is in contact with a side wall of one of the fins to a position of the upper surface of the isolation region which is in contact with a side wall of the other fin. In a cross section along the y-direction, the upper surface of the isolation region has a projecting shape.


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