The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2018
Filed:
Jan. 30, 2017
International Business Machines Corporation, Armonk, NY (US);
Ulvac, Inc., Kanagawa, JP;
Jack O. Chu, Manhasset Hills, NY (US);
Stephen M. Gates, Ossining, NY (US);
Masanobu Hatanaka, Yorktown Heights, NY (US);
Vijay Narayanan, New York, NY (US);
Deborah A. Neumayer, Danbury, CT (US);
Yohei Ogawa, Yorktown Heights, NY (US);
John Rozen, Hastings on Hudson, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SiHbased deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.