The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Aug. 10, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Hiroshi Maejima, Setagaya Tokyo, JP;

Koji Hosono, Fujisawa Kanagawa, JP;

Tadashi Yasufuku, Kanagawa, JP;

Noboru Shibata, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 2211/5621 (2013.01);
Abstract

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.


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