The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Feb. 17, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jun Seomun, Seoul, KR;

Insub Shin, Suwon-si, KR;

Kyungtae Do, Changwon-si, KR;

JungYun Choi, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1012 (2013.01); G11C 7/10 (2013.01); G11C 7/222 (2013.01);
Abstract

Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.


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