The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Apr. 28, 2016
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Hyun-Seok Hong, Asan-si, KR;

Hyo-Chul Lee, Asan-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 5/00 (2006.01); G09G 3/20 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
G09G 5/003 (2013.01); G09G 3/2096 (2013.01); H05K 1/0228 (2013.01); H05K 1/0296 (2013.01); H05K 1/147 (2013.01); H05K 1/181 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0281 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2330/06 (2013.01); G09G 2370/08 (2013.01); H05K 2201/058 (2013.01); H05K 2201/10128 (2013.01);
Abstract

A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.


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