The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

May. 18, 2016
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Sung In Kang, Yongin-si, KR;

Kyun Ho Kim, Yongin-si, KR;

Min Ho Park, Yongin-si, KR;

Ji Eun Jang, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/36 (2006.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G09G 3/3688 (2013.01); G09G 3/3696 (2013.01); G09G 2310/0267 (2013.01); G09G 2320/0219 (2013.01); G09G 2330/04 (2013.01); G09G 2330/06 (2013.01); G09G 2330/08 (2013.01); G09G 2330/12 (2013.01);
Abstract

A gate protection circuit includes: a clock signal generator to generate a plurality of gate clock signals; a gate driver to output gate signals based on the plurality of gate clock signals, the gate driver including a plurality of gate driving circuits cascaded to each other; and a monitoring line configured to transmit a feedback signal based on the plurality of gate clock signals via the plurality of gate driving circuits to the clock signal generator. The clock signal generator is to block generation of the plurality of gate clock signals in response to the feedback signal.


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