The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2018
Filed:
Sep. 11, 2014
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Kern Rim, San Diego, CA (US);
Stanley Seungchul Song, San Diego, CA (US);
Xiangdong Chen, Irvine, CA (US);
Raymond George Stephany, Austin, TX (US);
John Jianhong Zhu, San Diego, CA (US);
Ohsang Kwon, San Diego, CA (US);
Esin Terzioglu, San Diego, CA (US);
Choh Fei Yeap, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 17/50 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 17/5068 (2013.01); H01L 27/0207 (2013.01); G06F 17/5077 (2013.01); H01L 23/528 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.