The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jan. 13, 2016
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:
Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/10 (2016.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/064 (2013.01); G06F 3/0616 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7211 (2013.01);
Abstract

A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows of blocks. The controller may also read data sets from the memory dies. To do so, the controller may translate an abstract address to actual physical addresses, which may similarly identify actual blocks located in different rows of blocks.


Find Patent Forward Citations

Quick Actions:

Ravimohan, Narendhiran. (2018). Physical addressing schemes for non-volatile memory systems employing multi-die interleave schemes (U.S. Patent No. 9983829). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9983829

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…