The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Oct. 24, 2016
Applicants:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Socionext Inc., Yokohama-shi, Kanagawa, JP;

Inventors:

Bo Liu, Beijing, CN;

Weizhen Yan, Beijing, CN;

Lei Li, Beijing, CN;

Hao Chen, Beijing, CN;

Andrzej Radecki, Maidenhead, GB;

Assignees:

FUJITSU LIMITED, Kawasaki, JP;

SOCIONEXT INC., Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 (2006.01); H04L 27/01 (2006.01); H04L 27/06 (2006.01); H04L 25/03 (2006.01); H04L 27/26 (2006.01);
U.S. Cl.
CPC ...
H04L 27/01 (2013.01); H04L 25/03159 (2013.01); H04L 27/06 (2013.01); H04L 27/2647 (2013.01); H04L 27/2657 (2013.01); H04L 25/03273 (2013.01); H04L 27/265 (2013.01); H04L 27/2672 (2013.01);
Abstract

A channel equalization and tracking apparatus and method and a receiver. The apparatus includes: a Fourier transforming unit configured to transform a received time-domain signal into a frequency-domain signal; a compensating and equalizing unit configured to perform phase compensation and frequency-domain equalization on the signal outputted by the Fourier transforming unit by using one time of multiplication according to time delay information and an equalizer coefficient; a deciding unit configured to decide the equalized signal; and a channel tracking unit configured to track a channel according to the signal outputted by the Fourier transforming unit and an error signal obtained by the deciding unit. With embodiments of the present disclosure, not only complexity and hardware demands of the whole system are lowered, but also performance of the system is not affected.


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