The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

May. 05, 2016
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Christopher Mayer, Dover, MA (US);

David J. McLaurin, Raleigh, NC (US);

Christopher W. Angell, Cary, NC (US);

Sudhir Desai, Mansfield, MA (US);

Steven R. Bal, Cary, NC (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/091 (2006.01); H03L 7/093 (2006.01); H04B 7/0413 (2017.01); H03L 7/087 (2006.01); H03L 7/23 (2006.01); H03L 7/197 (2006.01); H03L 7/089 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03L 7/087 (2013.01); H03L 7/0891 (2013.01); H03L 7/091 (2013.01); H03L 7/093 (2013.01); H03L 7/23 (2013.01); H03L 7/235 (2013.01); H04B 7/0413 (2013.01); H04L 7/0331 (2013.01);
Abstract

Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.


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