The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Apr. 30, 2013
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Martin Vielemeyer, Villach, AT;

Walter Rieger, Arnoldstein, AT;

Martin Pölzl, Ossiach, AT;

Gerhard Nöbauer, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H03K 17/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/66477 (2013.01); H01L 29/1087 (2013.01); H01L 29/407 (2013.01); H01L 29/41766 (2013.01); H01L 29/78 (2013.01); H01L 29/7813 (2013.01); H01L 2924/0002 (2013.01); H03K 17/04 (2013.01);
Abstract

A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.


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