The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Oct. 30, 2015
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd, Singapore, SG;

Inventor:

Akira Ito, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 29/0649 (2013.01); H01L 29/512 (2013.01); H01L 29/7838 (2013.01);
Abstract

An Ultra Thin Body and Box (UTBB) fully depleted silicon on insulator (FDSOI) field effect transistor (FET) employing a split gate topology is provided. A gate dielectric layer is disposed beneath a gate structure and in contact with a channel layer of the device. The gate dielectric layer contains two portions, a thin portion and a thick portion. The thin portion is arranged and configured to reduce a trans-conductance of the device, while a thick portion is arranged and configured to increase the break down voltage of the device. The device further contains a bulk region that can be electrically connected to voltage source to provide control over the threshold voltage of the device.


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