The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Apr. 20, 2016
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Fausto Piazza, Grenoble, FR;

Sebastien Lagrasta, La Terrasse, FR;

Raul Andres Bianchi, Myans, FR;

Simon Jeannot, Grenoble, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11546 (2017.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 27/11521 (2017.01); H01L 49/02 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/11541 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11546 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28035 (2013.01); H01L 21/28273 (2013.01); H01L 21/32055 (2013.01); H01L 21/32133 (2013.01); H01L 27/0629 (2013.01); H01L 27/11521 (2013.01); H01L 28/60 (2013.01); H01L 29/4916 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 21/823468 (2013.01); H01L 27/11541 (2013.01);
Abstract

An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.


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