The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Jan. 09, 2017
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Herb He Huang, Shanghai, CN;

Clifford Ian Drowley, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11543 (2017.01); H01L 27/11521 (2017.01); H01L 21/311 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 27/11524 (2017.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11543 (2013.01); H01L 21/26513 (2013.01); H01L 21/28273 (2013.01); H01L 21/31111 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 29/66825 (2013.01);
Abstract

A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first source terminal formed of a material and connected to a first source, a first drain terminal formed of the material and connected to a first drain, a first gate overlapping a portion of the substrate that is between the first source and the first drain, and a first dielectric layer between the first gate and the substrate. The second transistor includes a control gate formed of the material and overlapping a part of the substrate that is positioned between a second source and a second drain, a second dielectric layer between the control gate and the substrate, a floating gate extending through the second dielectric layer to contact a doped region in the substrate, and an insulating member positioned between the control gate and the floating gate.


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