The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Sep. 13, 2017
Applicant:

Atp Electronics Taiwan Inc., Taipei, TW;

Inventors:

Tieh-Chin Hsieh, Taipei, TW;

Yu-Yin Kuo, Taipei, TW;

Hsi-Yang Huang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 23/50 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/56 (2013.01); H01L 23/293 (2013.01); H01L 23/3114 (2013.01); H01L 23/50 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/03552 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05016 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06551 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A method for manufacturing a memory having at least one stacked integrated circuit chip is firstly to remove a plurality of transitional weld structures from a first IC chip. A varied insulation layer is then formed on the first IC chip. The varied insulation layer is then processed by a laser beam to form a plurality of metal-disposed portions. A plurality of chip-conductive structures are then formed on the metal-disposed portions. A plurality of manufactured weld structures is formed on the chip conductive structures. A second IC chip having a plurality of original weld structures is then provided to the first IC chip. The original weld structures of the second IC chip are connected to the chip conductive structures of the first IC chip to form a stacked IC chip. The stacked IC chip is then mounted onto a memory substrate component to form a memory having the stacked IC chip.


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