The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Dec. 20, 2016
Applicants:

Imec Vzw, Leuven, BE;

Katholieke Universiteit Leuven, Leuven, BE;

Inventors:

Vikas Dubey, Leuven, BE;

Eric Beyne, Heverlee, BE;

Jaber Derakhshandeh, Tienen, BE;

Assignees:

IMEC vzw, Leuven, BE;

Katholieke Universiteit Leuven, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 23/49827 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0601 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01074 (2013.01);
Abstract

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.


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