The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

May. 24, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Dirk Ahlers, München, DE;

Gilles Delarozee, Grünwald, DE;

Daniel Schleisser, München, DE;

Christopher Spielman, Redford, MI (US);

Thomas Stoek, Buxtehude, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/00 (2006.01); H01L 23/52 (2006.01); H02M 7/5387 (2007.01); H02M 1/084 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 21/4825 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49562 (2013.01); H02M 1/084 (2013.01); H02M 7/53871 (2013.01); B60Y 2200/91 (2013.01);
Abstract

A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.


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