The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Jan. 15, 2014
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Chikaaki Kodama, Tokyo, JP;

Koichi Nakayama, Kanagawa-ken, JP;

Toshiya Kotani, Tokyo, JP;

Shigeki Nojima, Kanagawa-ken, JP;

Fumiharu Nakajima, Kanagawa-ken, JP;

Hirotaka Ichikawa, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/5072 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 23/528 (2013.01); H01L 2924/0002 (2013.01);
Abstract

According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.


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