The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2018

Filed:

Mar. 13, 2017
Applicant:

Invensense, Inc., San Jose, CA (US);

Inventors:

Jong Il Shin, San Jose, CA (US);

Peter Smeys, San Jose, CA (US);

Jongwoo Shin, Pleasanton, CA (US);

Assignee:

INVENSENSE, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 7/00 (2006.01); B06B 1/06 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00301 (2013.01); B06B 1/06 (2013.01); B81B 7/007 (2013.01); B81B 2201/0271 (2013.01); B81C 2203/036 (2013.01);
Abstract

Provided herein is a method including bonding a first oxide layer on a handle substrate to a second oxide layer on a complementary metal oxide semiconductor ('CMOS'), wherein the fusion bonding forms a unified oxide layer including a diaphragm overlying a cavity on the CMOS. The handle substrate is removed leaving the unified oxide layer. A piezoelectric film stack is deposited over the unified oxide layer. Vias are formed in the piezoelectric film stack and the unified oxide layer. An electrical contact layer is deposited, wherein the electrical contact layer electrically connects the piezoelectric film stack to an electrode on the CMOS.


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