The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Dec. 18, 2015
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Victor Yu Liu, Oakland, CA (US);

Yufei Wang, Holmdel, NJ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/24 (2006.01); H04L 12/751 (2013.01); H04L 29/14 (2006.01); H04L 12/437 (2006.01); H04B 10/038 (2013.01); H04L 12/715 (2013.01); H04L 12/707 (2013.01); H04L 12/703 (2013.01); H04J 14/02 (2006.01); H04L 12/735 (2013.01);
U.S. Cl.
CPC ...
H04L 41/0654 (2013.01); H04B 10/038 (2013.01); H04L 12/437 (2013.01); H04L 41/12 (2013.01); H04L 41/145 (2013.01); H04L 45/02 (2013.01); H04L 45/22 (2013.01); H04L 45/28 (2013.01); H04L 45/64 (2013.01); H04L 69/40 (2013.01); H04J 14/0287 (2013.01); H04L 45/1283 (2013.01);
Abstract

A method comprising identifying a physical ring in a physical layer of a network according to a logical ring in a logical layer of the network, wherein the logical ring is formed from a plurality of nodes interconnected by a plurality of logical links, and wherein the physical ring is formed from at least the plurality of nodes interconnected by a first plurality of physical links, computing a plurality of cross cord paths across the physical ring, and mapping the logical ring onto the physical layer to provide dual physical link failure survivability by determining primary paths and secondary paths for the plurality of logical links over the physical ring and the plurality of cross cord paths such that a secondary path of a first of the plurality of logical links is non-overlapping with a primary path of a second of the plurality of logical links.


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