Clock and data recovery apparatus and method of the same

Abstract

An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.