The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9973187 B1

PDF
Full Text
Expired
Date of Patent:
May. 15, 2018

Filed:

Dec. 16, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Harshat Pant, San Diego, CA (US);

Aditya Vummannagari, San Clemente, CA (US);

Yeshwant Kolla, Wake Forest, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03K 17/22 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 17/223 (2013.01); H03K 3/037 (2013.01);
Abstract

A power on reset circuit including an inverter powered by a first power domain, the inverter including a data input coupled to a power rail of a second power domain; logic circuitry coupled with an output of the inverter, the logic circuitry having a control signal output; and wherein, during a power up operation, the first power domain powers up before the second power domain powers up. Upon power up of the first power domain, the inverter can output a high signal to the logic circuitry and output a low signal to the logic circuitry in response to power up of the second power domain. The logic circuitry is further configured to output a first value for a control signal in response to the first power domain powering up and configured to output a second value for the control signal in response to the second power domain powering up.


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