The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Sep. 14, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Animesh Paul, Bangalore, IN;

Jingcheng Zhuang, San Diego, CA (US);

Xinhua Chen, San Diego, CA (US);

Ravi Sridhara, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 23/00 (2006.01); H03K 25/00 (2006.01); H03K 5/156 (2006.01); H03K 21/02 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); H03K 21/02 (2013.01);
Abstract

Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.


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