The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2018

Filed:

Jan. 30, 2014
Applicant:

Linear Technology Corporation, Milpitas, CA (US);

Inventors:

Michael Keith Mayes, Nevada City, CA (US);

Todd Stuart Kaplan, Grass Valley, CA (US);

David Edward Bliss, Loomis, CA (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 3/02 (2006.01); G05F 1/10 (2006.01); H02M 1/44 (2007.01); H02M 3/07 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/44 (2013.01); H02M 3/07 (2013.01); H03M 1/0818 (2013.01); H03M 1/1245 (2013.01); H03M 3/368 (2013.01); H03M 3/496 (2013.01);
Abstract

An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.


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